Level shifting in data processing apparatuses is a commonly applied technique. U.S. published patent applications 2003/0179032, 2005/0077919 and 2005/0122820 each disclose level shifting circuits in integrated digital devices. Traditionally, a dual power supply digital device, for example a non-volatile flash digital device, requires dedicated circuitry for gathering external information at a certain logic reference voltage level, typically referenced to VDDQ (i.e., the voltage of the input buffers coupled to the I/O pads of the device), and for translating the voltage level to a lower logic reference voltage level. This lower voltage level corresponds to regulated power supply voltage VDDIN.
Digital devices like DRAMs, SRAMs, EPROMs, Flash-EEPROMs and similar devices, commonly supporting a 3 V power supply voltage, and are being integrated with smaller size features and with thinner dielectric layers. These digital devices include an optimized area occupancy of core logic circuitry employing transistors designed for functioning at a down converted regulated supply voltage of the core circuitry, for example 1.8 V. This has led to the integration on the chip of a down converter of an externally applied power supply voltage that may vary from about 2.7 V to about 3.6 V to a regulated core supply voltage of about 1.8 V. Such a down converting circuit commonly includes a switching mode voltage regulator capable of regulating the down converted core supply voltage with high precision.
The two externally applied power supply voltages, namely VDD and VDDQ, could be applied to the digital device with a certain time lag, one with respect to the other one. In particular, the VDDQ voltage could be applied with a certain delay as compared to VDD. Should this occur, information input to the digital device may be conveyed to the core of the digital device in an unpredictable manner because of an incorrect powering of the I/O interfacing circuitry during power on, resulting in unpredictable consequences.
FIG. 1 is a basic circuit diagram showing the down converter that converts the externally applied power supply voltage VDD to a regulated core supply voltage VDDIN=1.8, and the input interfacing circuit for an I/O input pad INPAD_N of the digital device. The dedicated interfacing circuit basically functions as a latch-type voltage translator. If INPAD_N=0, then the replicated logic on the IN_N node will be 0, referenced to the internally regulated core supply voltage VDDIN. When INPAD_N=VDDQ, the input logic value 1 will be replicated on the IN_N node, referenced to the internally regulated internal core supply voltage VDDIN.
Generally, the ranges of the two externally applied power supply voltages may typically be as follows:
VDDQmin = 1.65 VVDDQmax = 3.6 VVDDmin = 2.7 VVDDmax = 3.6 V
In contrast, VDDIN can be assumed as practically stable at the regulated value of 1.8 V by virtue of the integrated switching mode down converter regulator that generates it.
As noted, problems may arise if VDD is present, and therefore VDDIN is also present, but the second power supply voltage VDDQ that powers the I/O buffers is not yet present. In this case, the logic level present on IN_N becomes unpredictable (floating). Such an accidental condition may be considered even more undesirable if the I/O pad in question is the one in which, for example, a write enable command WE_N is applied when the digital device is a memory device, or a global reset signal (RPM) is applied to the digital device. In both of these cases, the devices may have undesirable behaviors.